1. Field of the Invention
Exemplary embodiments of the present invention relate to a nonvolatile memory and an operation method of the same.
2. Description of the Related Art
Memory devices are divided into volatile memory devices and nonvolatile memory devices, depending on whether or not data stored therein are maintained when power supply is cut off. More specifically, the data stored in volatile memory devices are erased when power supply is cut off. Volatile memory devices may include DRAM and SRAM. In contrast, the data stored in nonvolatile memory devices are maintained even though power supply is cut off. An example of a nonvolatile memory device is a flash memory device.
FIG. 1 is a diagram illustrating parasitic capacitances occurring in a bit line of a nonvolatile memory.
Referring to FIG. 1, a coupling capacitor Cc is formed by coupling occurring between an even bit line BLe and an odd bit line BLo. Furthermore, a ground capacitor Cg is formed by coupling occurring between the even bit line BLe and a ground, and another ground capacitor Cg is formed by coupling occurring between the odd bit line BLo and a ground. In general, the coupling capacitor Cc formed by the coupling occurring between the bit lines BLe and BLo is about nine times larger than the ground capacitor Cg formed by the coupling occurring between the bit lines BLe and BLo and the ground.
FIGS. 2A and 2B are diagrams illustrating a process in which a bit line is precharged and recovered in a conventional nonvolatile memory before a program operation.
Referring to FIG. 2A, an even bit line BLe and an odd bit line BLo are coupled to corresponding cell strings 210 and 220, respectively. Furthermore, a bit line precharge unit 230 is provided to precharge the even bit line BLe and the odd bit line BLo. Furthermore, a bit line selection unit 240 is configured to electrically couple a bit line selected between the even bit line BLe and the odd bit line BLo to a page buffer unit 250.
Referring to FIG. 2A, a process in which the bit lines BLe and BLo are precharged will be described. First, an even precharge signal PCGe and an odd precharge signal PCGo become a high level to turn on transistors T1 and T2, and a precharge voltage applied to a virtual power terminal VIRPWR is supplied to the even bit line BLe and the odd bit line BLo. In FIG. 2A, arrows (a) and (b) indicate that currents are supplied to the bit lines BLe and BLo. In this case, since the even bit line BLe and the odd bit line BLo are simultaneously precharged, influence caused by a coupling capacitor Cc is not significant.
Referring to FIG. 2B, after the bit lines BLe and BLo are precharged, a bit line which is selected between the even bit line BLe and the odd bit line BLo, so as to be controlled by the page buffer unit 250, is electrically coupled to an output node PB_OUT of the page buffer unit 250, and an unselected bit line maintains the same state as the previous state (e.g., a precharged state). During an even page operation, the even bit line BLe becomes the selected bit line, and during an odd page operation, the odd bit line BLo becomes the selected bit line. Hereafter, it is assumed that the even bit line BLe is the selected bit line. Since the even bit line BLe is the selected bit line, an even selection signal SELe is activated to a high level, and an odd selection signal SELo is deactivated to a low level. Furthermore, the even precharge signal PCGe is deactivated to a low level, and the odd precharge signal PCGo maintains a state in which it is activated to a high level.
The output node PB_OUT of the page buffer unit 250 has a voltage level which is changed by inputted data. When the inputted data is program data (data which is to program a memory cell), the voltage level of the output node PB_OUT becomes a low level. When the inputted data is not program data, that is, when the inputted data is inhibition data, the voltage level of the output node PB_OUT becomes a high level. Therefore, the directions of currents flowing in the bit lines BLe and BLo, respectively, may be set as described in the following two cases—cases (1) and (2)—.
Case (1): Since the output node PB_OUT of the page buffer 250 becomes a low level when the inputted data is program data, the current of the selected bit line BLe flows in a direction (c), and the selected bit line BLe is discharged to a low level. Meanwhile, the current of the unselected bit line BLo flows in a direction (e). In this case, the currents of the selected bit line BLe and the unselected bit line BLo flow in the opposite directions. This has the effect of charging the coupling capacitor Cc. During this period, a relatively large peak current may be consumed.
Case (2): Since the output node PB_OUT of the page buffer becomes a high level when the inputted data is not program data, the current of the selected bit line BLe flows in a direction (d), and the current of the unselected bit line BLo flows in the direction (e). In this case, since the currents of the selected bit line BLe and the unselected bit line BLo flow in the same direction, a large peak current may not be consumed.
Although only one page coupled to one even bit line and one odd bit line is shown in FIGS. 2A and 2B, the above-described case (1) may occur simultaneously in all the even and odd bit lines BLe and BLo of the nonvolatile memory device. In this case, when currents flow in directions to charge a large number of coupling capacitors Cc, a large number of peak currents may be consumed inside the nonvolatile memory. The period in which case (1) takes place may represent a period in which the largest peak current is consumed in the entire operation of the nonvolatile memory. At this time, the power of the nonvolatile memory may be destabilized by an excessive peak current. As a result, an operation fail may occur.